1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method of the same, and more particularly to a device structure of bipolar transistor having a fine emitter area and base area and capable of integrating to high density and manufacturing method of the same.
2. Prior Art
FIG. 1A to FIG. 1F are sectional views showing a method of manufacturing a conventional bipolar transistor, in particular, an NPN transistor in the sequence of steps, and FIG. 2A to FIG. 2F are plan views of FIG. 1A to FIG. 1F, respectively. FIG. 1A is a sectional view along line A--A in FIG. 2A, and FIG. 1B to FIG. 1F are also sectional views at same position as line A--A in FIG. 2A.
As shown in FIG. 1A and FIG. 2A, a part of a P type semiconductor substrate 1 is selectively oxidized so that a field region 2 is formed by thermal oxidation using a silicon nitride film 3 as mask. Reference numeral 2' is a pad oxide film.
Consequently, as shown in FIG. 1B and FIG. 2B, after removing the silicon nitride film 3 from the surface of the substrate 1, using the resist formed by photolithographic technology as mask, an N type impurity, especially, phosphorus is injected by ion implantation. Then, after removing the resist, heat treatment is conducted to form an N.sup.+ collector draw-out region 4 having a junction depth of 1 to 1.5 .mu.m.
Then, as shown in FIG. 1C and FIG. 2C, using other resist as mask, boron is injected by ion implantation as a P type impurity, and after removing the resist, heat treatment is conducted to form a P type element separation region 5. In succession, by using photo resist as mask, phosphorus is injected by using a high acceleration ion implantation apparatus of 1 to 1.5 mega-electron-volts (MeV), and an N well region 6 is formed. After removing the photo resist, by injecting boron in the entire surface of the substrate 1, a base diffusion layer 7 is formed in a range enclosed by the field region 2. In this process, similar boron is injected also onto the collector draw-out region 4, but since the concentration difference is more than 100 times, it has almost no effect.
Next, as shown in FIG. 1D and FIG. 2D, part of the pad oxide film 2' of the collector part and emitter part is removed by dry or wet etching, using photo resist formed by photolithographic technology as mask, and openings (contacts) 8', 8" are formed. After removing the resist, polycrystalline silicon film 9 of 1000 to 2000 .ANG. is formed by chemical vapor deposition (CVD). Then, arsenic ions (As) of 1.times.10.sup.16 to 3.times.10.sup.16 cm.sup.-2 are implanted into the entire surface of the substrate 1 and injected into the polycrystalline silicon film 9.
As shown in FIG. 1E and FIG. 2E, using a new photo resist 13 as mask, other area than specified regions for emitter and collector of the polycrystalline silicon film 9 is removed. In succession, by ion implantation of high concentration boron, using photo resist as mask, an external base region 17 of low resistance is formed. In this case, the energy of ion implantation must be set to such a level that impurity ions may not pass through the field thermal oxide film.
Then, as shown in FIG. 1F and FIG. 2F, after removing the resist, non-doped oxide film and boron- and phosphorus-doped oxide film (BPSG) are sequentially formed by chemical vapor deposition, and an interlayer film 19 is formed. By heat treatment of furnace annealing or lamp annealing of 900 to 1000.degree. C., an emitter diffusion layer 16 is formed.
Successively, by etching the interlayer film 19 formed of BPSG/SiO.sub.2 on specified region by using the resist formed by photolithographic technology as mask, an opening (contact) for metal wiring connection is formed. Finally, removing the resist, an aluminum alloy containing copper is formed by sputtering method, and by dry etching using the resist as mask, a metal wiring 18 is formed.
A conventional manufacturing method by using a self-matching technology is described below. As shown in FIG. 3A, an N.sup.+ buried diffusion layer 24 is formed on a P type semiconductor substrate 1, and after forming an N.sup.- type epitaxial layer 23 on the semiconductor substrate 1 by epitaxial technology, a pad oxide film 2' is formed, and a silicon nitride film 3 is formed on its surface.
Then, as shown in FIG. 3B, a resist is formed on the nitride film 3 by a known photolithographic technology, and, using it as mask, the silicon nitride film 3 and pad oxide film 2' are etched. Using the remaining pad oxide film 2' and silicon nitride film 3 as mask, the N.sup.- type epitaxial layer 23 is selectively etched, and a groove 25 is formed at a position for forming an element separation oxide film.
Next, as shown in FIG. 3C, by thermal oxidation, a thick element separation oxide film 2 made of silicon oxide film layer is formed in the groove 25. After removing the nitride film used as anti-oxidation mask, although not shown, by ion implantation of phosphorus by using resist as mask, a collector draw-out region is formed same as in prior art 1.
After removing the pad oxide film 2' as shown in FIG. 3D, a first polycrystalline silicon film 9 is formed on the entire surface of the substrate 1. By thermal oxidation, a polycrystalline silicon oxide film 26 is formed on the surface of the first polycrystalline silicon film 9.
Consequently, as shown in FIGS. 3D and 3E, after ion implantation of boron into the first polycrystalline silicon film 26, by anisotropic etching by using a resist 13 formed by photolithographic technology as mask, the polycrystalline silicon oxide film 26 and polycrystalline silicon film 9 are etched successively.
Then, as shown in FIG. 3F, after thinly oxidizing the surface exposed by anisotropic dry etching, a CVD oxide film 27 is formed on the entire surface of the substrate. At this time, in the end portion of contacting side of the polycrystalline silicon film 9, boron is diffused outward of the polycrystalline silicon film 9, and an external base diffusion region 17 of high concentration is formed.
As shown in FIG. 3G, by anisotropic etching, the CVD oxide film 27 is etched, and a side wall 28 of the CVD oxide film 27 is formed. By ion implantation of boron through an opening narrowed by this side wall 28, a base region 7 is formed by heat treatment.
Next, as shown in FIG. 3H, after forming a second polycrystalline silicon film 29 on the entire surface of the substrate, arsenic ions are injected into the second polycrystalline silicon film 29, and the second polycrystalline silicon film 29 is etched by using the patterned resist as mask. In succession, by heating in a non-oxidizing atmosphere, the arsenic is diffused into the base region 7 from within the second polycrystalline silicon film 29, and an emitter diffusion layer 16 is formed.
In the prior at shown in FIG. 3A through FIG. 3H, however, although a fine emitter area or base area can be preserved, and, in addition to high integration, it is possible to improve electric characteristics due to decrease of parasitic capacity and realize low power consumption. However, there is a problem that because the device structure is complicated in this prior art, the number of processes is about 1.5 times more than that of FIGS. 1A to 1F, and the process conditions are severe, the yield is low, and hence the cost is higher.
In this prior art, although the merit of realizing the tiny dimension smaller than the minimum dimension at excellent controllability by the photolithographic technology being employed is outstanding, at further smaller size, the film thickness of the polycrystalline silicon at the emitter opening becomes thicker, and the base width is extended until the arsenic injected by ion implantation diffuses in the polysilicon and reaches the base region. The emitter resistance is also higher, and the characteristics deteriorate on the whole, and high speed device forming is disabled. As the countermeasure, at the present, arsenic-doped polycrystalline silicon is used, but as compared with ion implantation, uniformity in the surface of substrate is poor, which may lead to fluctuations of characteristics.
In the prior art shown in FIG. 1A to FIG. 1F and FIG. 2A to FIG. 2F, from its device structure, the number of processes is small and a high yield is expected, but the base area is determined automatically by the deviation margin between the opening (contact) and metal for metal wiring, and interval between metal and metal, and at the present it is about two times as wide as in prior art shown in FIGS. 3A to 3H, and it is not easy to form finely, and hence it is inferior in the aspects of low power consumption and high integration. However, the emitter area depends on the lithographic technology being employed.